Most of the computing and electronic devices manufactured nowadays use non-volatile memories for permanent storage of data. In these memories, data is not deleted even after the removal of the power supply. In other words, data once stored in these memories is retained irrespective of the status of the power supply to the memory.
Conventionally used non-volatile memories are read only memories (ROMs), programmable read only memories (PROMs), erasable programmable read only memories (EPROMs), one-time-programmable EPROMs, flash memories, and magneto-resistive read only memories (MRAM). Typically, a single non-volatile memory is made up of one or more memory arrays, which in turn are made up of many electrically programmable memory cells.
As commonly known, digital information is stored in a non-volatile memory in a combination of binary forms ‘zero’ or ‘one’. This value (‘zero’ or ‘one’) is determined by the state of each memory cell included in the memory array of the non-volatile memory. To clearly understand the structure of a convention non-volatile memory, consider a memory made up of a single memory array and the memory array including many memory cells connected to each other. A portion of such a memory array 100 is shown in FIG. 1. Although memory array 100 is shown to include just four memory cells 102a, 102b, 102c, and 102d, it can include many more similar cells connected to each other. The state of each memory cell in memory array 100 is determined using bit line ‘S’, which is shown to be connected to the source terminals of all the transistors of the four memory cells.
As shown in FIG. 1, a single memory cell 102a includes a transistor 104 and a half transistor 106 (other memory cells also have the same structure). Transistor 104 is the ‘select’ transistor and is used to ‘select’ memory cell 102a during programming or read operations of memory cell 102a. Half transistor 106 is the programmable or data storage element of memory cell 102a. As depicted, the gate of transistor 104 is connected to a select line ‘R1’ and the gate of half transistor 106 is connected to a program line ‘C1’. Whenever memory cell 102a is to be read, a potential is applied to C1, R1, and S, and the current flowing through ‘S’ depicts the state of memory cell 102a. For example, when memory cell 102a is in the ‘high’ state (or in a state corresponding to ‘one’), voltages applied to C1, R1, and S result in a non-zero current in the bit line ‘S’.
There are many known methods for programming a memory cell. In one such method, a high potential is applied to the gate dielectric layer of a transistor to cause its ‘breakdown’. Half transistor 106 shown in FIG. 1 is an example of one such transistor whose gate dielectric can be broken down by applying a high potential across its gate dielectric layer. The process of programming a memory cell is disclosed in detail in the following patents: U.S. Pat. No. 6,667,902 ‘Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric’ issued Dec. 23, 2003 to Kilopass Technologies, Inc; U.S. Pat. No. 6,822,888 ‘Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric’ issued Nov. 23, 2004 to Kilopass Technologies, Inc; and U.S. Pat. No. 6,671,040 ‘Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric’ issued Dec. 30, 2003 to Kilopass Technologies, Inc.
A detailed structure of a conventional one time programmable (OTP) memory cell 200 is shown in FIG. 2. As depicted, memory cell 200 includes an isolation layer 204 formed over a lightly doped P-type semiconductor substrate 202. Isolation layer 204 is assumed to be formed using silicon dioxide (SiO2) or many similar dielectric materials. Memory cell 200 further includes a field effect transistor 206 and a programmable element 208. Both field effect transistor 206 and programmable element 208 are enhancement MOS devices, and, as depicted, programmable element 208 is an MOS-type capacitor.
For description purposes, field effect transistor 206 is assumed to be an N-type transistor having a drain region 210, a source region 212, a gate insulator 214, and a conductive gate 216. As shown, drain region 210 and source region 212 are n+ doped regions, and gate insulator 214 is assumed to be an SiO2 layer overlying a channel region 218.
When a positive voltage is applied at conductive gate 216 (or in other words, when memory cell 200 is ‘selected’), an inversion layer 220 is formed at the upper surface of channel region 218. Inversion layer 220 electrically connects drain region 210 with source region 212, thus allowing the flow of electrons from source region 212 to drain region 210. Further, as shown, a bit line 222 (which is similar to bit line ‘S’ of FIG. 1) is connected to source region 212, and a select word line 224 (which is similar to select line ‘R1’ of FIG. 1) is connected to conductive gate 216. To ‘select’ transistor 206, proper voltages are applied to select word line 224 and program word line 232, and whenever current flows through inversion layer 220, a non-zero current flows through bit line 222, indicating that memory cell 200 is in the ‘high’ state or ‘one’ logic.
Further, as shown in FIG. 2, programmable element 208 has a semiconductor body 226, an insulating layer 228, and a conductive layer 230. Insulating layer 228 is assumed to be made of SiO2 (similar to gate insulator 214). Typically, the thickness of insulating layer 228 is the same or less than the thickness of gate insulator 214.
As shown, a program word line 232 is connected to conductive layer 230, which can be made of poly silicon or any other high conductive material. During programming or read operation of memory cell 200, a positive voltage is applied to conductive layer 230 through program word line 232. Typically, to program memory cell 200 as a permanent ‘high’ (state corresponding to logic ‘one’), a high voltage is applied to conductive layer 230 which causes insulating layer 228 to ‘breakdown’ permanently. After the breakdown process is over, whenever a voltage is applied to conductive layer 230, a current starts to flow through programmable element 208 to drain 210 and finally to source 212. In this case, a conductive path is provided through insulating layer 228 for the flow of charge carriers.
The structure of memory cell 200 described above has a drawback. An effective p-n junction diode is formed at the breakdown site under conductive gate 230. Due to this, degradation of the memory cell takes place when the high voltage is applied to conductive layer 230 during programming.
In light of the drawback mentioned above, there is a need for an OTP memory cell which overcomes the limitation of the conventional memory cell without added process cost, i.e. the fabrication of the memory cell should preferably follow standard CMOS process.